Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemented in Wireless Local Area Network (WLAN), Radio Frequency Identification (RFID) tags and Bluetooth controller as the default choice for security services in its application. Substitution box (S-box) is a non-linear transformation and the core of AES implementation which consumed most of the power in AES hardware. This paper presents a low-complexity design methodology for the S-box/ Inverse S-box (Inv S-box) implemented in Field-Programmable Gate Array (FPGA) using composite field arithmetic and Quartus II as a tool to obtain simulation results through Verilog Hardware Description Language (HDL). This design utilized 94 slices with the hardware cost of the S-box/InvS-box is about 172 logic gates, with the power consumption of 31mW and the throughput is 1.6Gbps obtained through calculation. The design is suitable for the portable device application which requires data security with a low area and power consumption.


    Access

    Download


    Export, share and cite



    Title :

    AES S-Box/ Inv S-Box Optimization Using FPGA Implementation


    Contributors:

    Publication date :

    2017-11-30


    Remarks:

    Journal of Telecommunication, Electronic and Computer Engineering (JTEC); Vol 9, No 3-8: Recent Trend in Electronic, Computing and Communication; 133-136 ; 2289-8131 ; 2180-1843


    Type of media :

    Article (Journal)


    Type of material :

    Electronic Resource


    Language :

    English



    Classification :

    DDC:    629



    High-Performance IIR Filter Implementation Using FPGA

    Vijay, Vallabhuni / Seshagiri Rao, V. R. / Chaitanya, Kancharapu et al. | IEEE | 2022



    FPGA Implementation of Data Fusion Algorithms

    YADAV, S. SREEKRISHNA / MITTAL, VIKAS | IEEE | 2019


    FPGA Implementation of a FIR Filter Using Residue Arithmetic

    Loonawat, G. / Siferd, R. E. / IEEE; Dayton Section et al. | British Library Conference Proceedings | 1996


    Implementation Of LEM2 algorithm On FPGA

    Narsale, Nikhil / Agarwal, Vanita | IEEE | 2019