It is necessary to insert a switching delay time in pulse width modulation(PWM) voltage-fed inverters to avoid the short through of phase bridge. This causes well known dead time effect which distorts the output voltage and current. This paper puts forward a new three-level dead-time compensation method, which compensates dead time, turn on and off delay and forward voltage drop. A three-level inverter hardware platform was built based on FPGA and DSP, and the relevant experiment has been done on the 30kW three-phase induction motor. Experimental results verified the feasibility and correctness of the algorithm.


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    Title :

    A novel dead-time compensation strategy of three-level inverter


    Contributors:
    Guo Jing (author) / Gong Xuegeng (author) / Zhao, Feng (author) / Wen, Xuhui (author)


    Publication date :

    2014-08-01


    Size :

    1347643 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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