As a step towards a real-time signal aperture radar (SAR) correlator, custom very large scale integration (VLSI) architectures are developed. Considering the extremely short word length of the data, we derive three architectures with massive parallelism in bit space. Unlike frequency methods, no. degradation is introduced during convolution. Optimized for time and space, they are highly suited to VLSI implementation, and a small architecture with 80 taps operating at 10 MHz has been built using an FPGA.
VLSI architecture for SAR data compression
IEEE Transactions on Aerospace and Electronic Systems ; 38 , 2 ; 427-440
2002-04-01
2729045 byte
Article (Journal)
Electronic Resource
English
VLSI architecture for SAR data compression
Tema Archive | 2002
|PAPERS - VLSI Architecture for SAR Data Compression
Online Contents | 2002
|Data Compression and VLSI Implementation
NTRS | 1993
|NTRS | 1985
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