Recently, highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adder/subtracter has been presented based on redundant bit representation (RBR) for the operands digits where it has been shown that only 24 (30) minterms are needed to implement the two-step recoded TSD (the one-step nonrecoded) addition for any operand length. In this paper, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products.


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    Title :

    Recoded and nonrecoded trinary signed-digit multipliers designs using redundant bit representations


    Contributors:
    Cherri, A.K. (author) / Alam, M.S. (author)


    Publication date :

    1998-01-01


    Size :

    685665 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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