A methodology for designing radiation tolerant CMOS APS SOC image sensors is presented. It is based on the experimental results of test chips that had been designed, fabricated, and characterized. Details of the basic building blocks of a proposed design are presented. The proposed design is in a 0.35-/spl mu/m CMOS standard process. The radiation tolerance level could be up to 30 Mrad (Si) total dose of ionizing radiation. The proposed methodology has the potential of yielding highly integrated, highly functional, highly compact, low power, radiation tolerant, cost effective CMOS APS SOC image sensors.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Design of radiation tolerant CMOS APS system-on-a-chip image sensors


    Contributors:
    Eid, E.-S. (author) / Ay, S.U. (author) / Fossum, E.R. (author)


    Publication date :

    2002-01-01


    Size :

    1112557 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    7.0402 Design of Radiation Tolerant CMOS APS System-on-a-Chip Image Sensors

    Institute of Electrical and Electronics Engineers | British Library Conference Proceedings | 2002



    0.25mum Radiation Tolerant CMOS technology

    Rodde, K. / European Space Agency | British Library Conference Proceedings | 2002



    0.25 micron radiation tolerant CMOS technology

    Roedde, K. | Tema Archive | 2002