This article describes the design of a random number generator of low-cost rapid prototyping implemented in a reconfigurable FPGA device. The architecture of the generator is also described. The results for random number generation speed per clock cycle. To validate the operation of the random number generator, a series of tests proposed by the NIST “National Institute of Standards and Technology” were carried out, according to the results obtained, the proposed generator works as a pseudo-random number generator. These were verified the test of Maurer’s “Universal Statistical” test and the binary matrix rank test. Similarly, the results of these tests are shown, where a P value ≥ 0.01 is considered, which indicates that the sequence is random with 99.9% confidence. Also, the details of the proposed design are shown together with the results of the simulation carried out in ISE 14.7 and the occupation it has in the FPGA.
Design and Implementation in FPGA a Random Number Generator of 10 bits validated by NIST Maurer’s “Universal Statistical” and Binary Matrix Rank tests
2022-12-05
646942 byte
Conference paper
Electronic Resource
English
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