Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.
Independent synchronizer for digital decoders
NASA Tech Briefs ; 5 , 1
1980-08-01
Miscellaneous
No indication
English
NTRS | 1970
|Double Indexing Synchronizer - To Amplify the Synchronizer Capacity
SAE Technical Papers | 2012
|