Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.


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    Title :

    Independent synchronizer for digital decoders


    Contributors:

    Published in:

    Publication date :

    1980-08-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




    Digital synchronizer Patent

    Anderson, T. O. | NTRS | 1970


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