Program converts cell-net data into logic-gate models for use in test and simulation programs. Input consists of either Place, Route, and Fold (PRF) or Place-and-Route-in-Two-Dimensions (PR2D) layout data deck. Output consists of either Test Pattern Generator (TPG) or Logic-Simulation (LOGSIM) logic circuitry data deck. Designer needs to build only logic-gate-model circuit description since program acts as translator. Language is FORTRAN IV.


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    Title :

    CADAT network translator


    Contributors:

    Published in:

    Publication date :

    1981-04-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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