Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.


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    Title :

    Large-Constraint-Length, Fast Viterbi Decoder


    Contributors:
    Collins, O. (author) / Dolinar, S. (author) / Hsu, In-Shek (author) / Pollara, F. (author) / Olson, E. (author) / Statman, J. (author) / Zimmerman, G. (author)

    Published in:

    Publication date :

    1990-04-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English





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