Future digital avionics systems will make extensive use of VHSIC and semi-custom devices to gain multifold increase in processing power and capability. Mission/operational requirements dictate high availability with capability to detect 98 percent of all faults, isolate 90 percent of these faults to a line replaceable module (LRM), or 95 percent of the faults to two LRMs or less. System requirements also demand rapid detection of faults and isolation of the faulty module(s). This paper present an integrated approach called the Maintenance And Diagnostic System (MADS) developed at TRW Military Electronics Division to meet the above challenges. The MADS concept achieves the above goals by devining a Module Maintenance Node (MMN) chip set for each LRM in the system and the design for testability concepts for hardware. The MMN aids parallel, high speed testing of LRMs, with the ability to isolate the fault(s) to a module/chip level while incurring less than 10 percent overhead. It uses the concepts of scan set design, pseudorandom test vector generation, output response compression, and separate scan set loops to test the SSI-MSI lgic on the LRM. It also provides capability to store interim test results and run-time fault information to isolate the 'hard to reproduce' failures; and performs verification of interchip and intermodule wiring.


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    Title :

    Design for testability for future digital avionics systems


    Additional title:

    Prueffaehiger Schaltungsentwurf fuer die digitale Avionik


    Contributors:


    Publication date :

    1986


    Size :

    5 Seiten, 6 Bilder, 1 Tabelle, 5 Quellen


    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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