In one embodiment, a system determines a plurality of memory controllers available at a central processing unit (CPU) chipset of an autonomous driving system (ADS) for an autonomous driving vehicle (ADV), the CPU chipset having a plurality of processing cores. The system partitions the plurality of memory controllers at the CPU chipset into N regions. The system determines a shared cache memory at the CPU chipset that is shared among the plurality of processing cores. The system partitions the shared cache memory into N segments according to the N regions. The system configures CPU chipset settings to associate each memory controller in the N regions to a segment of the shared cache memory in the respective region. Data and/or instruction sets are accessed by the CPU chipset from a memory controller through a segment of the cache memory that is associated to the memory controller.


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    Title :

    LOW LATENCY MEMORY ACCESS FOR CPUS IN AUTONOMOUS VEHICLES


    Contributors:
    YU ZHENWEI (author)

    Publication date :

    2025-05-15


    Type of media :

    Patent


    Type of material :

    Electronic Resource


    Language :

    English


    Classification :

    IPC:    G06F ELECTRIC DIGITAL DATA PROCESSING , Elektrische digitale Datenverarbeitung / B60W CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION , Gemeinsame Steuerung oder Regelung von Fahrzeug-Unteraggregaten verschiedenen Typs oder verschiedener Funktion



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