A fault code analyzer for a vehicle includes a fault code memory device configured to store a plurality of active and inactive fault codes for the vehicle and a priority processor coupled to the memory device. The priority processor is configured to: prioritize each fault code within the plurality of active and inactive fault codes; determine a first root cause fault code, the first root cause fault code corresponding to the highest prioritized fault code; determine a first set of interaction fault codes, the first set of interaction fault codes relating to the first root cause fault code; and provide the first root cause fault code and the first set of interaction fault codes to an interface device of a user.


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    Title :

    Fault code hierarchy system


    Contributors:

    Publication date :

    2016-12-06


    Type of media :

    Patent


    Type of material :

    Electronic Resource


    Language :

    English


    Classification :

    IPC:    G07C TIME OR ATTENDANCE REGISTERS , Zeit- oder Anwesenheitskontrollgeräte / B60W CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION , Gemeinsame Steuerung oder Regelung von Fahrzeug-Unteraggregaten verschiedenen Typs oder verschiedener Funktion / G05B Steuer- oder Regelsysteme allgemein , CONTROL OR REGULATING SYSTEMS IN GENERAL



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