A Digital Down Converter (DDC) is presented based on square wave local oscillators facilitating a multiplier-less implementation with no constraints on the sampling frequency. The DDC includes a pseudo multi-rate SINC low pass filter which exhibits better performance compared to the standard multi-stage sinc filter. The pseudo multi-rate SINC filter can be implemented with a unique cascaded integrator comb (CIC) filter to obtain the same improved performance. A 90nm CMOS design with 8 bit inputs clocked at 400MHz demonstrates a flexible, very low power/size DDC architecture for single chip digital receiver applications.
Multiplier-less Digital Down Converter in 90nm CMOS technology
2011-07-01
568784 byte
Conference paper
Electronic Resource
English
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