In this paper, a pulse width amplitude modulation multiplication scheme, that uses a novel flipped voltage follower (FVF) based current switch is presented. Simulations performed in Hspice with the standard AMI 0.5μm CMOS process shows a system with dynamic range of ±140 mV for both input signals with a maximum gain error of 1.1%. The circuit works with VDD = 3 V and a power consumption of 2.2 mW. The multiplier has a bandwidth of 16 kHz.


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    Title :

    Pulse Width Amplitude Modulation Based CMOS Multiplier


    Contributors:
    Astro, R (author) / Gómez, H (author) / Salinas, J (author) / Diaz-Sanchez, A (author)


    Publication date :

    2010-09-01


    Size :

    225025 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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