The wide bandgap devices have brought new opportunities for motor drives. With higher switching frequency, the common-mode voltage (CMV) issue wm be worse due to high dv/dt. The balanced inverter is a cost-effective solution to the CMV issue. The balanced inverter is proposed recently, but the impact of power-loop stray inductance for the printed circuit board has not been explored. In order to provide crucial information for layout optimization, this paper investigates the effects of stray inductance in the power loop on the balanced inverter for high voltage high power applications. Simulation has been conducted under four scenarios, and results have been presented.
Study of Performance of Balanced Inverter under Influence of Power Loop Stray Inductance
2020-06-01
381339 byte
Conference paper
Electronic Resource
English
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