The authors report on the concepts and technologies required to develop, integrate, and test the Pave Pillar architecture in an avionics system. Hardware and software issues relating to multiprocessing, multitasking, and real-time reconfiguration are discussed. The issues involved in developing and integrating the VHSIC avionic modular processors (VAMPs), high-speed data bus networks, and Ada software are examined. An avionic hot bench simulation was integrated to provide a closed-loop real-time test set-up called the integrated testbed (ITB) facility. The configuration and test setup for the common avionics modules were selected to provide a realistic environment and to be as close to the defined Pave Pillar architecture as possible.<>


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    Title :

    Pave Pillar in-house research final report


    Contributors:
    Blair, J.L. (author) / Powers, P. (author)


    Publication date :

    1992-01-01


    Size :

    794605 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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    Pave Pillar avionics designed for dependability

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    High Speed Bus for Pave Pillar Applications

    Ludvigson, M. T. / Goldman, P. C. | SAE Technical Papers | 1986