The problem of parallel implementation of the square-root Kalman filters is addressed. At the system level, our approach is to apply systolic-type VLSI processor arrays as basic building blocks to accelerate the matrix operations required in each iteration. To maximize the parallelism, we also exploit an inter-array pipelining scheme through the overlapping of execution between successive processor arrays. We estimate that with (5n2 + r2 + 8nr + n + 3r)/2 processors, it would take max[(4n + 2r, 2n + 4r-2)] time units to complete one Kalman filter iteration, where n is the dimension of the underlying state space model and r is the dimension of the input vector.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Parallel VLSI Implementation of the Kalrman Filter


    Contributors:
    Sung, Tze-Yun (author) / Hu, Yu-Hen (author)

    Published in:

    Publication date :

    1987-03-01


    Size :

    3151771 byte




    Type of media :

    Article (Journal)


    Type of material :

    Electronic Resource


    Language :

    English



    Adaptive Filter and Its VLSI Implementation

    Sakai, H. / Tanaka, K. | British Library Online Contents | 1994


    VLSI implementation of parallel Kalman filters

    TRAVASSOS, R. / ANDREWS, A. | AIAA | 1982


    Optimization of Digital Filter Structures for VLSI Implementation

    Saromaeki, T. / Ritoniemi, T. | British Library Online Contents | 1993


    An Efficient Pipelined VLSI Implementation of Rank Order Filter

    Chen, C. T. / Chen, L. G. / Chiueh, T. D. et al. | British Library Conference Proceedings | 1994


    An efficient pipelined VLSI implementation of rank order filter

    Chun-Ta Chen / Liang-Gee Chen / Tzi-Dar Chiueh et al. | IEEE | 1994