The problem of parallel implementation of the square-root Kalman filters is addressed. At the system level, our approach is to apply systolic-type VLSI processor arrays as basic building blocks to accelerate the matrix operations required in each iteration. To maximize the parallelism, we also exploit an inter-array pipelining scheme through the overlapping of execution between successive processor arrays. We estimate that with (5n2 + r2 + 8nr + n + 3r)/2 processors, it would take max[(4n + 2r, 2n + 4r-2)] time units to complete one Kalman filter iteration, where n is the dimension of the underlying state space model and r is the dimension of the input vector.
Parallel VLSI Implementation of the Kalrman Filter
IEEE Transactions on Aerospace and Electronic Systems ; AES-23 , 2 ; 215-224
01.03.1987
3151771 byte
Aufsatz (Zeitschrift)
Elektronische Ressource
Englisch
Adaptive Filter and Its VLSI Implementation
British Library Online Contents | 1994
|VLSI implementation of parallel Kalman filters
AIAA | 1982
|Optimization of Digital Filter Structures for VLSI Implementation
British Library Online Contents | 1993
|An Efficient Pipelined VLSI Implementation of Rank Order Filter
British Library Conference Proceedings | 1994
|