Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.
Rounding Technique for High-Speed Digital Signal Processing
NASA Tech Briefs ; 7 , 3
1983-08-01
Miscellaneous
No indication
English