Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.
Rounding Technique for High-Speed Digital Signal Processing
NASA Tech Briefs ; 7 , 3
01.08.1983
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Englisch
High Speed 16 bit Digital Signal Processor
British Library Online Contents | 1993
The Distribution of Rounding Error
NTIS | 1970
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