Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.


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    Title :

    Scheduled Peripheral Component Interconnect Arbiter


    Contributors:

    Publication date :

    2015-02-10


    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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