Utilizing the Karatsuba algorithm, we achieve comprehensive efficiency in high-precision floating-point multiplication. This design optimizes by reducing partial-product generation, resulting in an impressive performance boost of up to 30% compared to conventional methods. The process involves handling sign, exponent, and significand components, utilizing Karatsuba for significand multiplication, normalizing data, adding exponents, and rounding results. This hardware module, designed for digital systems and ASICs, demonstrates an exceptional throughput of up to 10,000 floating-point multiplications per second. Its parallel operation ensures precision, with a margin of error of just 0.01%. The achieved results successfully validate the module's efficiency and precision, with a 99.9% success rate in numerical computations. The Karatsuba algorithm showcases a speedup of up to 5 times faster than traditional methods in mantissa multiplication. A three-stage pipelining approach shows the effectiveness of the Karatsuba algorithm in large-scale numerical computations, with a reduction in processing time of 60%. FPGA-based design and implementation of this floating-point multiplier offer exceptional speed, capable of performing 500,000 multiplications per second. This speed makes it invaluable in DSP, cryptography, and scientific computing applications, significantly enhancing performance and precision in numerical simulations.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Implementation of a High-Performance 32-Bit Floating Point Multiplier via the Karatsuba Algorithm


    Additional title:

    Smart Innovation, Systems and Technologies



    Conference:

    Congress on Control, Robotics, and Mechatronics ; 2024 ; Warangal, India February 03, 2024 - February 04, 2024



    Publication date :

    2024-10-31


    Size :

    14 pages





    Type of media :

    Article/Chapter (Book)


    Type of material :

    Electronic Resource


    Language :

    English





    A quasi-floating point algorithm for combinational logic

    Xinggan Zhang / Zhaoda Zhu | IEEE | 1996


    Provably Correct Floating-Point Implementation of Well Clear Avionics Concepts

    M. M. Moscato / N. B. F. Ferreira / L. Titolo et al. | NTIS | 2023


    A Provably Correct Floating-Point Implementation of Well Clear Avionics Concepts

    Mariano M Moscato / Nikson Bernardes Fernandes Ferreira / Laura Titolo et al. | NTRS


    CMOS VLSI implementation of a digital logarithmic multiplier

    Ramaswamy, S. / Siferd, R.E. | IEEE | 1996