In order to achieve fast decoding and improve the throughput, this paper uses the polar code to encode the spin transfer torque MARAM (STT-MRAM) channel. Based on the Fast-SSC algorithm, a (256, 220) hardware architecture is designed, including the controller, processing element, Kronecker product and memory module. This paper reduces the complexity of data process by splitting the data of nodes, and reduces the memory bandwidth by increasing the reusability of data. The decoder is synthesized on Stratix V 5SGXEA7N2F45C2, the decoding latency is 0.68us, and it can achieve 375 Mbps at 167 MHz.


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    Title :

    Design of Fast-SSC Decoder for STT-MRAM Channel


    Additional title:

    Lect.Notes Social.Inform.


    Contributors:
    Wu, Qihui (editor) / Zhao, Kanglian (editor) / Ding, Xiaojin (editor) / Cui, Jianming (author) / Bao, Zengxiang (author) / Zhang, Xiaojun (author) / Guo, Hua (author) / Chen, Geng (author)

    Conference:

    International Conference on Wireless and Satellite Systems ; 2020 ; Nanjing, China September 17, 2020 - September 18, 2020



    Publication date :

    2021-02-28


    Size :

    10 pages





    Type of media :

    Article/Chapter (Book)


    Type of material :

    Electronic Resource


    Language :

    English




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