In order to achieve fast decoding and improve the throughput, this paper uses the polar code to encode the spin transfer torque MARAM (STT-MRAM) channel. Based on the Fast-SSC algorithm, a (256, 220) hardware architecture is designed, including the controller, processing element, Kronecker product and memory module. This paper reduces the complexity of data process by splitting the data of nodes, and reduces the memory bandwidth by increasing the reusability of data. The decoder is synthesized on Stratix V 5SGXEA7N2F45C2, the decoding latency is 0.68us, and it can achieve 375 Mbps at 167 MHz.
Design of Fast-SSC Decoder for STT-MRAM Channel
Lect.Notes Social.Inform.
International Conference on Wireless and Satellite Systems ; 2020 ; Nanjing, China September 17, 2020 - September 18, 2020
28.02.2021
10 pages
Aufsatz/Kapitel (Buch)
Elektronische Ressource
Englisch
British Library Conference Proceedings | 2002
|NTRS | 1986
|Kraftfahrwesen | 2011
|NTRS | 1986
|MRAM Design Limiations Dictated by Thermally Activiated Reversal
British Library Conference Proceedings | 2002
|