Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
ERROR CORRECTION HARDWARE WITH FAULT DETECTION
FEHLERKORREKTUR-HARDWARE MIT FEHLERERKENNUNG
MATÉRIEL DE CORRECTION D'ERREUR AVEC DÉTECTION DE DÉFAUT
03.03.2021
Patent
Elektronische Ressource
Englisch
IPC: | G06F ELECTRIC DIGITAL DATA PROCESSING , Elektrische digitale Datenverarbeitung / B60W CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION , Gemeinsame Steuerung oder Regelung von Fahrzeug-Unteraggregaten verschiedenen Typs oder verschiedener Funktion / G11C Statische Speicher , STATIC STORES |
Principles of error detection and error correction codes
NTRS | 1971
|Detection and Correction for Measurement Error
SAE Technical Papers | 1965
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