Aspects of the present disclosure provide a method generally including obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions, applying a compression scheme to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and data field of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes, and storing the compressed BIST patterns.


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    Titel :

    BUILT-IN SELF-TEST ENHANCEMENTS


    Beteiligte:
    VERMA GAURAV (Autor:in) / TANDON SAKSHAM (Autor:in)

    Erscheinungsdatum :

    26.09.2024


    Medientyp :

    Patent


    Format :

    Elektronische Ressource


    Sprache :

    Englisch


    Klassifikation :

    IPC:    G01R Messen elektrischer Größen , MEASURING ELECTRIC VARIABLES / B60L PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES , Antrieb von elektrisch angetriebenen Fahrzeugen / G11C Statische Speicher , STATIC STORES / G06F ELECTRIC DIGITAL DATA PROCESSING , Elektrische digitale Datenverarbeitung



    MULTIFUNCTIONAL ELECTRODE SEPARATOR ASSEMBLIES WITH BUILT-IN REFERENCE ELECTRODES AND THERMAL ENHANCEMENTS

    GAO JING / KOCH BRIAN J / XIAO XINGCHENG et al. | Europäisches Patentamt | 2023

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