This paper presents the FPGA implementation of half-order digital integrator configured in lattice wave digital structure. The optimal lattice wave coefficients for 3rd and 5th structure are obtained using the Driving Training-Based Opti-mization(DTBO) algorithm to approximate integration operator. The Simulink model of the resulting lattice wave structure shows less susceptibility compared to the traditional IIR realization for finite precision data representation. The radix $-2^{r}$ encoding based multiplication is utilized for the efficient multiplier-less implementation of the suggested lattice wave design on FPGA using Xilinx system generator for DSP.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    FPGA Implementation of Lattice-Wave Half-Order Digital Integrator using Radix-$2^{r}$ Digit Recoding


    Beteiligte:
    Sharma, Abhay (Autor:in) / Gupta, Mridul (Autor:in) / Rawat, Tarun (Autor:in)


    Erscheinungsdatum :

    01.12.2022


    Format / Umfang :

    561745 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




    Low-latency Sliding-window Recoding

    Tasdemir, Elif / Tomoskozi, Mate / Salah, Hani et al. | IEEE | 2021


    Parallel higher-radix signed-digit arithmetic using shared content addressable memory (Invited Paper) [3211-78]

    Alam, M. S. / Indian Institute of Technology, Madras / SPIE | British Library Conference Proceedings | 1997


    One-Step High-Radix Signed-Digit Arithmetic Units Based on Classified Joint Spatial Encoding

    Cherri, A. / IEEE | British Library Conference Proceedings | 1998


    Fluid amplifier digital integrator

    Rose, R. K. | TIBKAT | 1966