With the advancement of integrated circuit technology, nanoscale latches operating in space environments are more sensitive to single-event multiple-node upset. Based on the polarity design, this article proposes an N-polarity cell (N-cell) and a P-polarity cell (P-cell), which can block the propagation of double-node upset (DNU). Then, a low-overhead DNU self-recoverable latch (LODRL) is proposed, which consists of a DNU self-recoverable (DNUR) core structure and a clock-gated inverter. Compared with state-of-the-art DNUR latches, the proposed LODRL has an average reduction of 17.07%, 52.62%, 31.23%, and 78.81% in area, power consumption, delay, and power–delay–area product (PDAP), respectively. Furthermore, a high-performance DNU self-recoverable and triple-node-upset tolerant latch (DRTTL) is proposed, which consists of a DNUR core, a clock-gated inverter, and an interlocked structure. Compared with these advanced triple-node-upset (TNU)-tolerant latches, the DRTTL has an average reduction of 17.7%, 41.91% and 56.25% in power consumption, delay, and PDAP, respectively. The DRTTL is also insensitive to a high-impedance state and process, voltage, and temperature variations, exhibits a large critical charge, and can achieve complete DNU self-recovery and 90% TNU self-recovery. Therefore, the DRTTL features low overhead and high performance, which is suitable for applications in aerospace environments.
High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications
IEEE Transactions on Aerospace and Electronic Systems ; 60 , 5 ; 6550-6561
01.10.2024
4353970 byte
Aufsatz (Zeitschrift)
Elektronische Ressource
Englisch
A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch
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