In this paper, efficient hardware implementations of soft demappers, which use three low complexity methods to compute log-likelihood ratio (LLR), are proposed for WiFi7 4096-QAM. The first method adopts an approximated function that employs only absolute value, addition, and subtraction operations to reduce complexity. The second method is a piecewise linear function for all the bits. The third method is a hybrid function between the first and the second which uses the piecewise linear function for b0 and b6 bits and the approximated function for other bits. By using modified functions to avoid division operations, we proposed efficient hardware implementations to support not only 4096-QAM but also lower QAMs for each of the functions. The complexities of the three hardware implementations are 5.2 Kgates, 11.4 Kgates and 22.2 Kgates for the approximated, hybrid, and piecewise linear functions respectively when synthesized with 5 nm CMOS technology for 480 MHz operation. The estimated powers are 204 uW, 598 uW, and 1510 uW for the approximated, hybrid, and piecewise linear functions respectively for an EHT packet of 4096-QAM with 160 MHz bandwidth and channel model D. The required SNR of the piecewise linear function is 0.3~0.4 dB better than other two functions for packet error rate of 10 %. The proposed soft demapper hardware with approximated function is appropriate for power and area optimized PHYs, and one with the piecewise linear function is appropriate for performance optimized PHYs based on the experimental results.
Efficient Hardware Implementation of Soft Demapper for WiFi7 4096-QAM
10.10.2023
1186712 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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