In this paper, a quasi-floating point algorithm is presented that is implemented with a combinational logic circuit for processing data at high speed in real-time. It is an approximate algorithm for computing module of a complex datum and nonlinear mapping of data. The circuit of quasi-floating point computing consists of normalizing unit, simple combinational logic computing unit and fixed-point restoring unit. If the remaining bit number N is 8, the relative error is less than 0.01.
A quasi-floating point algorithm for combinational logic
01.01.1996
170855 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
A Quasi-Float Point Algorithm for Combination Logic
British Library Conference Proceedings | 1996
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