Coder/decoder constructed on single integrated-circuit chip. Handles data in variety of formats at rates up to 300 Mbps, correcting up to 3 errors per data block of 256 to 512 bits. Helps reduce cost of transmitting data. Useful in many high-data-rate, bandwidth-limited communication systems such as; personal communication networks, cellular telephone networks, satellite communication systems, high-speed computing networks, broadcasting, and high-reliability data-communication links.


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    Titel :

    Triple-Error-Correcting Codec ASIC


    Beteiligte:
    Jones, Robert E. (Autor:in) / Segallis, Greg P. (Autor:in) / Boyd, Robert (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    01.06.1994



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch





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