Aeroflex Colorado Springs has developed a monolithic 16M-bit SRAM radiation-hardened to greater than 100 krad(Si) total ionizing dose on TSMC's 0.18/spl mu/m shallow trench isolation (STI) CMOS line using minimally invasive process intervention. Both single event latchup (SEL) and single event upset (SEU) due to charged particle strikes are mitigated by a combination of circuit design techniques, error detection and correction (EDAC), and enhanced layout design rules. The 16M-bit SRAM is SEL immune to greater than 105 MeV-cm/sup 2//mg. The SEU error rate is less than 2.9/spl times/10/sup -16/ errors/bit-day.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Next generation radiation-hardened SRAM for space applications


    Contributors:
    Hafer, C. (author) / Mabra, J. (author) / Slocum, D. (author) / Kalkur, T.S. (author)

    Published in:

    Publication date :

    2006-01-01


    Size :

    336944 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    A Radiation Hardened 16-Mb SRAM for Space Applications

    Hoang, Tri / Ross, Jason / Doyle, Scott et al. | IEEE | 2007


    Design considerations for next generation radiation hardened SRAMs for space applications

    Haddad, N. / Rockett, L. / Doyle, S. et al. | Tema Archive | 2005


    Design Considerations for Next Generation Radiation Hardened SRAMs for Space Applications

    Haddad, N. / Rockett, L. / Doyle, S. et al. | British Library Conference Proceedings | 2005


    Commercially fabricated radiation hardened 4Mbit SRAM

    Hafer, C. / Slocum, D. / Mabra, J. et al. | IEEE | 2004