Aeroflex Colorado Springs has developed a monolithic 16M-bit SRAM radiation-hardened to greater than 100 krad(Si) total ionizing dose on TSMC's 0.18/spl mu/m shallow trench isolation (STI) CMOS line using minimally invasive process intervention. Both single event latchup (SEL) and single event upset (SEU) due to charged particle strikes are mitigated by a combination of circuit design techniques, error detection and correction (EDAC), and enhanced layout design rules. The 16M-bit SRAM is SEL immune to greater than 105 MeV-cm/sup 2//mg. The SEU error rate is less than 2.9/spl times/10/sup -16/ errors/bit-day.
Next generation radiation-hardened SRAM for space applications
2006 IEEE Aerospace Conference ; 8 pp.
2006-01-01
336944 byte
Conference paper
Electronic Resource
English
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