Aeroflex Colorado Springs has developed a monolithic 16M-bit SRAM radiation-hardened to greater than 100 krad(Si) total ionizing dose on TSMC's 0.18/spl mu/m shallow trench isolation (STI) CMOS line using minimally invasive process intervention. Both single event latchup (SEL) and single event upset (SEU) due to charged particle strikes are mitigated by a combination of circuit design techniques, error detection and correction (EDAC), and enhanced layout design rules. The 16M-bit SRAM is SEL immune to greater than 105 MeV-cm/sup 2//mg. The SEU error rate is less than 2.9/spl times/10/sup -16/ errors/bit-day.


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    Titel :

    Next generation radiation-hardened SRAM for space applications


    Beteiligte:
    Hafer, C. (Autor:in) / Mabra, J. (Autor:in) / Slocum, D. (Autor:in) / Kalkur, T.S. (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    01.01.2006


    Format / Umfang :

    336944 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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