Digital implementations for both the recoding and the addition steps for the signed-digit numbers require four or more logic levels (AND-OR) or (OR-AND) and at least 23 logic gates for each output bit. In this paper, a much simpler nonrecoding signed-digit adder is presented. Its hardware implementation requires much fewer logic gates and inputs lines than that for the recoded signed-digit one for the same number of logic levels.
Recoded versus nonrecoded signed-digit number based digital parallel arithmetic: a case study
1995-01-01
263626 byte
Conference paper
Electronic Resource
English
Recoded Versus Non Recoded Signed-Digit Number Based Digital Parallel Arithmetic: A Case Study
British Library Conference Proceedings | 1995
|Recoded and Non-Recoded Trinary Signed-Digit Multipliers Designs Using Redundant Bit Representations
British Library Conference Proceedings | 1998
|Optoelectronics Recoded Trinary Signed Digit Adder Using Optical Correlators
British Library Conference Proceedings | 1997
|