Digital implementations for both the recoding and the addition steps for the signed-digit numbers require four or more logic levels (AND-OR) or (OR-AND) and at least 23 logic gates for each output bit. In this paper, a much simpler nonrecoding signed-digit adder is presented. Its hardware implementation requires much fewer logic gates and inputs lines than that for the recoded signed-digit one for the same number of logic levels.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    Recoded versus nonrecoded signed-digit number based digital parallel arithmetic: a case study


    Beteiligte:
    Cherri, A.K. (Autor:in)


    Erscheinungsdatum :

    01.01.1995


    Format / Umfang :

    263626 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Recoded Versus Non Recoded Signed-Digit Number Based Digital Parallel Arithmetic: A Case Study

    Cherri, A. K. / IEEE / Dayton Section| IEEE et al. | British Library Conference Proceedings | 1995


    Recoded and Non-Recoded Trinary Signed-Digit Multipliers Designs Using Redundant Bit Representations

    Cherri, A. / Alam, M. / IEEE | British Library Conference Proceedings | 1998


    Optoelectronics recoded trinary signed-digit adder using optical correlators

    Cherri, A.K. / Habib, M.K. / Alam, M.S. | IEEE | 1997


    Optoelectronics Recoded Trinary Signed Digit Adder Using Optical Correlators

    Alam, M. / Cherri, A. / Habib, M. et al. | British Library Conference Proceedings | 1997