Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.


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    Titel :

    Generating Weighted Test Patterns for VLSI Chips


    Beteiligte:

    Erschienen in:

    Erscheinungsdatum :

    01.01.1990



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch


    Schlagwörter :


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