Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.


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    Titel :

    Cascaded VLSI Chips Help Neural Network To Learn


    Beteiligte:
    Duong, Tuan A. (Autor:in) / Daud, Taher (Autor:in) / Thakoor, Anilkumar P. (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    01.12.1993



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch


    Schlagwörter :



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